`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/09/03 22:48:26
// Design Name: 
// Module Name: test_top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module test_top();
    reg clk;
    reg rst;
    reg rst_d;
    always #10 clk <= ~clk;
    
    initial 
    begin
        clk = 0;
        rst = 1;
        #50
        rst = 0;
    end
    
    reg [3:0]   randnum_noseed;
    
    always@(posedge clk) begin
        randnum_noseed <= $random(); //不指定随机种子
    end
    

    wire ready;
    wire [3:0] data;
    reg valid;
    
    reg [3:0] data_reg;
    wire handshake;
    assign data = randnum_noseed;
    assign handshake = ready&&valid;

    always @(posedge clk)
    begin
        if (rst ==1'b1)
        begin
            data_reg <= 1;
        end
        else 
        begin
            data_reg <= handshake == 1'b1 ? randnum_noseed:data_reg;  //握手成功后发送数据
        end
    end
    
    //握手模块
    always @(posedge clk)
    begin 
        if(rst == 1'b1)
        begin
            valid <= 0;
        end
        else 
        begin
            valid <= $random(); 
        end
    end
    
    wire ready_d;
    wire [3:0] data_d;
    wire valid_d;
    
    dest dest(.clk(clk),.rst(rst_d),.ready(ready_d),.data(data_d),.valid(valid_d));
    station sta(.clk(clk),.rst(rst_d),.ready_s(ready),.data_s(data),.valid_s(valid),.ready_d(ready_d),.data_d(data_d),.valid_d(valid_d));
    
    reg ready_d1;
    reg ready_d2;
    reg ready_d3;
    reg ready_d4;
    reg ready_d5;
    
    always @(posedge clk)
    begin 
        if(rst == 1'b1)
        begin
            ready_d1 <= 1;
            ready_d2 <= 1;
            ready_d3 <= 1;
            ready_d4 <= 1;
            ready_d5 <= 1;
        end
        else 
        begin
            ready_d1 <= ready_d;
            ready_d2 <= ready_d1;
            ready_d3 <= ready_d2;
            ready_d4 <= ready_d3;
            ready_d5 <= ready_d4;
        end
    end
 
    reg flag;
    
    always @(posedge clk)
    begin
        if (rst ==1'b1)
        begin
            rst_d <= 1;
            flag <= 1;
        end
        else 
        begin
            if (flag == 0)
            begin
                if ((ready_d + ready_d1 + ready_d2 + ready_d3) == 0)
                begin
                    rst_d <= 1;
                    flag <= 1;
                end
                else
                begin
                    rst_d <= 0;
                    flag <= 0;
                end
            end 
            else
            begin
                flag <= (ready_d + ready_d1 + ready_d2 + ready_d3) == 0 ? flag : 0;
                rst_d <= 0;
            end
        end
    end   
    
    
    
    
endmodule